The present disclosure relates generally to test systems, and more particularly to a system and method for improving communications between a device under test (DUT) and a tester.
The increasing functional complexity of electronic components and systems has made integrated circuit (IC) testing challenging, particularly under the constraints of making a continuous improvement in quality and a continuous reduction in cost. The cost of manufacturing a transistor continues to improve as predicted by Moore's Law. Test costs, however, have not generally followed the same price/performance curve as the transistor and are therefore becoming a higher percentage of the total manufacturing cost of a chip.
Today, manufacturers of automatic test equipment (ATE) offer test systems to address the increasingly complex task of testing advanced multi-function, ICs such as system-on-a-chip (SoC). However, many commercially available ATE systems are complex, proprietary, not easily flexible to meet changing test conditions, often require additional heat removal systems, and typically cost several million dollars, thereby making them unattractive for use in a cost driven manufacturing environment. Recently, many semiconductor manufacturers, and some ATE suppliers have introduced low cost test systems such as a very low cost tester (VLCT). The VLCT system may be used as a standalone test system, or used in combination with a conventional ATE system. The VLCT systems typically provide lower test costs, and are more flexible in meeting the changing test conditions, making them more attractive in the cost driven manufacturing environment.
VLCT systems may be used for performing mixed signal (e.g., analog and digital) testing, which may include radio frequency (RF) analog signals and high speed digital signals. However, due to cost considerations, many of the VLCT systems may provide a limited amount of performance, and may have a limited capacity. For example, some VLCT systems may have a limited data throughput for testing, e.g., the systems may include a clock that is limited to 30 megahertz (MHz) frequency. These VLCT systems may be unable to perform high speed digital signal data capture or data sourcing for testing high speed chips having clock rates greater than 30 MHz.
Some of these limitations may result in operating the VLCT at the lower clock speeds, e.g., 30 MHz, thereby increasing the time, and reducing the efficiency to test each DUT. The mismatch in clock speeds may cause problems in maintaining time synchronization between the VLCT and the DUT. The additional time needed for testing each DUT at the lower clock speed is magnified at the manufacturing process level when millions of DUT's may be tested in a day. As a result, some of the limitations of the VLCT systems may inadvertently slow down the production rate, and may contribute to an overall increase in the cost of testing.